STM32 MCU study notes
1, AHB system bus is divided into APB1 (36MHz) and APB2 (72MHz), of which 2>1, meaning APB2 connected to high-speed equipment
2, Stm32f10x.h is equivalent to reg52.h (there is a basic bit operation definition), and the other is stm32f10x_conf.h specifically controls the configuration of peripheral devices, that is, the role of the switch header file
3, HSE Osc (High Speed ​​External Oscillator) high-speed external crystal oscillator, generally 8MHz, HSI RC (High Speed ​​InternalRC) high-speed internal RC, 8MHz
4, LSE Osc (Low Speed ​​External Oscillator) low-speed external crystal oscillator, generally 32.768KHz, LSI RC (Low Speed ​​InternalRC) low-speed internal crystal oscillator, about 40KHz, providing watchdog clock and automatic wake-up unit clock source
5, SYSCLK clock source has three sources: HSI RC, HSE OSC, PLL
6, MCO[2:0] can provide 4 different clock synchronization signals, PA8
7. The GPIO looks like two diodes in reverse series are used as clamping diodes.
8. The bus matrix uses the rotation algorithm to arbitrate the system bus and DMA.
9, ICode bus, DCode bus, system bus, DMA bus, bus matrix, AHB/APB bridge
10. Before using a peripheral, the register RCC_AHBENR must be set to turn on the peripheral's clock.
11, the data bytes are stored in memory in little endian storage
12, the memory map is divided into 8 large blocks, each block is 512MB
13. One page of FLASH is 1K (small capacity and medium capacity), and the large capacity is 2K.
14. The system memory (SystemMemory) is locked by the ST company's factory configuration and cannot be edited by the user. It is used to reprogram the FLASH area. Therefore, we must program BOOT1 = 0 for the programming program, so that FLASH can be programmed by the embedded bootloader, such as interrupt vector table and code.
15, STM32 core voltage is 1.8V
16. There are three types of STM32 reset: system reset, power-on reset, and backup area reset. The system reset is reset except that the reset flag in RCC_CSR and the value in BKP are not reset. Trigger modes such as external reset, watchdog reset, software reset, etc.; power reset due to power-on/power-down reset of the external power supply or standby mode return. Reset except that the register value in BKP does not move, all others are reset; the trigger source of the backup area reset is software reset or VDD and VBAT are all powered down.
17. All I/O ports are floating input status after reset of the MCU
18, 68 maskable interrupt channels, 16 programmable priorities, 16 core interrupts, a total of 68 + 16 = 84 interrupts. The 103 series has only 60 interrupts, and the 107 series has 68 interrupts.
19, system startup starts from 0x00000004, 0x000 0000 is reserved
20, (NestedVectored Interrupt Controller) NVIC nested vector interrupt controller, divided into two types: preemptive priority (nestable) and interrupt priority (sub-priority, can not be nested). The two priorities are determined by 4 binary bits. There are 16 cases assigned:
21, 0 preemptive priority interrupt, can interrupt any interrupt preemption priority is non-zero interrupt; 1 preemptive priority interrupt, can interrupt any interrupt preemption priority is 2, 3, 4 interrupt ;......; constitutes interrupt nesting. If the preemption priorities of the two interrupts are the same, whoever appears first will respond first, and does not constitute nesting. If they appear together (or hang there and wait), it depends on which of their 2 children have higher priority. If the sub-priorities are the same, look at their interrupt vector positions. The location of the original interrupt vector is the final determinant! ! ! !
22. After power-on initialization, AIRC is initialized to 0, which is 16 preemptive priority. However, since all external channel interrupt priority control words PRI_n are 0, the preemptive priority is the same, so it cannot be nested at this time.
23, NVI has ISER [2] (Interrupt Set-Enable Registers), ICER [2] (Interrupt Clear-Enable Registers), ISPR [2] (Interrupt Set-Pending Registers), ICPR [2] (Interrupt Clear-Pending Registers), IABR [2] (AcTIve Bit Registers), IPR [15] (InterruptPriority Registers) definition. Where ISER and ICER are the interrupt enable and interrupt disable registers, respectively, write 1 to enable/disable interrupt. Why write 1? Why not use one register and two registers to indicate interrupt enable/disable status? Due to hardware, writing 0 is more complicated and may cause other bits to change state. Therefore, it is more reasonable to use 1 to indicate that opening or shutting down.
24, the interrupt flag needs to be manually cleared
25. General steps for configuring peripheral devices: 1. Turn on the port clock. 2. Define the initialization structure and initialize it. 3, call
26, the parity of the serial port: If it is parity, then USART_InitStructure.USART_WordLength= USART_WordLength_9b; the length of this data must be set to 9!
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