RF IC integrated design strategy for next-generation LTE base station transmitters
Upgrading from 3G to LTE-Advance poses many challenges to equipment and device suppliers of next-generation mobile communication infrastructure. The next generation of wireless devices are required to support wider signal bandwidths and more complex modulation methods, so that higher data rates can be obtained on various operating frequency bands deployed worldwide. Therefore, performance such as noise, signal linearity, power consumption, and form factor are very critical, and the requirements for these performances are also more stringent. In addition, component suppliers are also required to reduce the cost and size of components to support higher density applications.
The challenges faced by designers of radio frequency chips (RF ICs) will also become increasingly daunting, as integrated solutions must have or exceed the performance achieved by discrete components. When implementing discrete components, system designers can adopt different technologies (such as GaAs, Si Bipolar, or CMOS) to optimize the design. But for RF IC designers who want to provide higher integration through a single process technology, the biggest challenge in choosing the best process technology is flexibility.
In the base station's transmitter, the analog I / Q modulator is a key RF IC device that determines the noise floor and linearity of the transmitted signal path, and does not allow performance to be sacrificed to reduce size, power consumption, or cost.
Fortunately, SiGe BiCMOS process technology can achieve higher integration without sacrificing performance. These processes usually provide SiGe NPN transistors in multiple speed categories, and in some cases can also provide complementary high-performance PNP transistors that are twice (more often twice) the characteristic size of CMOS transistors. On this basis, MIM capacitors, thin film resistors and more important multilayer thick copper and aluminum metal films can also be added. These features can help designers implement multiple high-performance functional modules on a single chip, thereby greatly reducing power consumption, reducing size, and maintaining high performance. 
An important aspect of the transmitter board-level design is the synthesis and distribution of local oscillator clocks used in various up-conversion and down-conversion conversion circuits. The distribution of the local oscillator clock of the base station must maintain the phase consistency to all long-distance positions of the PCB, and must have low in-band noise, broadband noise, and total spurious noise. The performance of the mixer is the same as the local oscillator that drives it, so high-quality local oscillators are the key to improving the overall performance of the transmitter. In addition, small phase noise or spurious components on the local oscillator signal may introduce enough energy into the analog signal path, causing the transmitter to fail to meet some major cellular communication standards (MC-GSM, WCDMA, LTE, WiMAX ) The specified spurious interference index. These standards require a local oscillator frequency range of about 500MHz to close to 4GHz, which means that the layout design used for local oscillator clock distribution must be very careful. The trace length from the generation of the local oscillator to the final termination should be as short as possible, but if the local oscillator synthesizer must be fed to multiple different devices, this requirement is difficult to meet. One solution is to feed a common low-frequency reference clock to an independent PLL synthesizer near each local oscillator, but this will occupy a large PCB area.
By integrating an advanced fractional-N PLL and VCO, the ADRF670x series integrated modulator solves many of the above problems. The use of silicon-germanium technology allows the dynamic range of the quadrature modulator and mixer with built-in VCO to reach the industry-leading level, and has competitive performance, but the volume is significantly smaller than the external VCO / PLL solution. The VCO is implemented in the upper thick metal layer and can use high-Q on-chip inductors as part of the LC circuit. VCO capacitors are composed of MOS switch-type MIM capacitors, thus allowing the VCO to switch frequencies in a wide frequency range with low phase noise. Each time the PLL frequency is programmed, the frequency band is automatically adjusted, thus providing an independent and reliable solution. After the initialization is completed, the size of the frequency band should be selected to ensure that the device can work normally in the entire temperature range. The thick metal layer is also used to integrate an output balun with excellent reflection loss. The ADRF670x series consists of four members with overlapping frequency parameters, covering the frequency range and frequency band from 400MHz to 3GHz. Each member is defined according to the output Balun bandwidth on the 1dB and 3dB passbands. 
The ADRF670x and ADRF660x series fractional-N PLL designs are ideal for low phase noise 3G and 4G applications. These new cellular standards have dense signal constellations and require lower and lower local oscillator phase noise to achieve adequate performance. The traditional PLL synthesizer design uses an "integer N" architecture whose output frequency is an integer multiple of the phase discriminator frequency. To provide smaller frequency steps, the integer multiplication factor must be very large. A large amount of local oscillator phase noise originates from the reference path and is amplified by the PLL frequency multiplication factor, which will cause high in-band noise at the output of the PLL. The fractional-N PLL allows the output frequency to have smaller steps while keeping the total multiplier value low, so that the phase-noise amplification value can be reduced compared to the integer-N-frequency PLL.
Adjacent channel power ratio (ACPR) is an indicator to determine how much of the transmitted signal leaks into adjacent frequency bands. 3G standards like WCDMA have strict limits on out-of-band transmit power. The ACPR index of ADRF6702 is shown in Figure 3. The modulator provides highly linear output power and low noise, so it has an ACPR value better than -76dB at the -6dBm output point, which helps reduce the number of gain stages behind the modulator and makes the dynamic range in front of the end power amplifier stage circuit to reach maximum. 
The ADRF670x series devices integrate three LDO circuits, which can work under a single 5V power supply, thereby further simplifying user applications, reducing costs and circuit board area. LDO is used to provide stable power to the VCO, charge pump, and PLL incremental accumulation modulator. The + 5V power supply can be directly used for the IQ modulator to maximize the output power.
In high-density applications, the ADL670x can use the PLL to complete the internal synthesis of the local oscillator, while other devices can disable their PLL and use the common local oscillator from a master device.
The ADRF670x series products are designed to simplify the user interface and facilitate the connection with AD9122, the latest transmission digital-to-analog converter from ADI, and GaAs amplifiers (such as the ADL5320). (ADL5320 is a 0.25 watt high linearity amplifier that can drive power above 0dBm into the final power amplifier circuit.) These three compact ICs form a complete active IC device combination, which is the next generation of multi-carrier frequency Ideal for cellular wireless platforms.
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