74hc164 is the AND gate input, asynchronously clears the 8-bit serial-in and parallel-out shift register of the CLR.
　　 The input data is completely input by the A and B ports. When any of the A and B ports is low, the input data of the other port is shielded, and the state of the first trigger is set to 1 at the next clock pulse; A, B ports When either is high, the state of the flip-flop will be determined by the input data of the other port. If the clock rollover meets the minimum settling time, the input data will be read in as the clock high and low transitions, and the circuit is triggered by the rising edge, during which the clock level transitions from low to high.
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