This chapter introduces the basic elements of Verilog HDL, including identifiers, comments, values, compiler instructions, system tasks, and system functions. In addition, this chapter introduces two types of data in the Verilog hardware description language.
3.1 identifierThe identifier (idenTIfier) ​​in Verilog HDL can be any combination of letters, numbers, symbols, and _ (underscore) symbols, but the first character of the identifier must be a letter or an underscore. In addition, identifiers are case sensitive. Here are a few examples of identifiers:
Count
COUNT // is different from Count.
_R1_D2
R56_68
FIVE$
The escaped identifier (escaped idenTIfier) ​​can contain any printable character in an identifier. The escape identifier begins with a \ (backslash) symbol and ends with a blank (a blank can be a space, a tab character, or a newline character). Here are a few escape identifiers:
\7400
\.*.$
\{******}
\~Q
\OutGate is the same as OutGate.
This last example explains that in an escape identifier, backslashes and end spaces are not part of the escape identifier. That is, the identifier \OutGate and the identifier OutGate are identical.
Verilog HDL defines a set of reserved words, called keywords, which are used only in certain contexts. Appendix A lists all reserved words in the language. Note that only keywords with lowercase are reserved words. For example, the identifier always (this is a keyword) is different from the identifier ALWAYS (non-keyword).
In addition, the escape identifier is not exactly the same as the keyword. The identifier \iniTIal is different from the identifier iniTIal (this is a keyword). Note that this convention is different from those of escaped identifiers.
There are two forms of comments in Verilog HDL.
/* The first form: can be extended to multiple lines */
// The second form: at the end of the line.
3.3 formatVerilog HDL is case sensitive. That is to say, the identifiers with different capitalization are different. In addition, Verilog HDL is free-form, meaning that structures can be written across multiple lines or written in a single line. White space (new lines, tabs, and spaces) has no special meaning. The explanation is explained below by way of example.
Initial begin Top = 3' b001; #2 Top = 3' b011; end
Same as the following instructions:
Initial
Begin
Top = 3' b001;
#2 Top = 3' b011;
End
An identifier starting with a $ character indicates a system task or system function. The task provides a mechanism for encapsulating behavior. This mechanism can be called in different parts of the design. A task can return zero or more values. A function is the same as a task except that it can only return one value. In addition, the function is executed at time 0, ie no delay is allowed, and the task can be delayed.
$display ("Hi, you have reached LT today");
/* $display The system task is displayed in a new line. */
$time
//The system task returns the current simulation time.
System tasks and system functions are explained in detail in Chapter 10.
3.5 Compilation InstructionsSome identifiers starting with ` (backquotes) are compiler directives. When the Verilog language is compiled, specific compiler directives are valid throughout the compilation process (the compilation process can span multiple files) until other different compiler instructions are encountered. The complete standard compiler directives are as follows:
* `define, `undef
* `ifdef, `else, `endif
* `default_nettype
* `include
* `resetall
* `timescale
* `unconnected_drive, `nounconnected_drive
* `celldefine, `endcelldefine
3.5.1 `define and `undef
The `define directive is used for text substitution, much like the #define directive in C, such as:
`define MAX_BUS_SIZE 32
. . .
Reg [ `MAX_BUS_SIZE - 1:0 ] AddReg;
Once the `define directive is compiled, it is valid throughout the compilation process. For example, MAX_BUS_SIZE can be used by multiple files with the `define directive in another file.
The `undef command cancels the macro defined earlier. E.g:
`define WORD 16 //Create a text macro instead.
. . .
Wire [ `WORD : 1] Bus;
. . .
`undef WORD
// After the `undef compile directive, the macro definition of WORD is no longer valid.
3.5.2 `ifdef, `else and `endif
These compile instructions are used for conditional compilation as follows:
`ifdef WINDOWS
Parameter WORD_SIZE = 16
`else
Parameter WORD_SIZE = 32
`endif
During the compilation process, if a text macro named WINDOWS has been defined, the first parameter declaration is selected, otherwise the second parameter description is selected.
The `else program directive is optional for the `ifdef directive.
3.5.3 `default_nettype
This command is used to specify the type of wire network for an implicit wire network. That is, the types of wires that are not described are defined.
`default_nettype wand
The default net network defined by this instance is line and type. Therefore, if there are no wires described in any of the modules following this instruction, the net is assumed to be a line and type.
3.5.4 `include
The `include compiler directive is used to embed the contents of an embedded file. Files can be defined either by relative path names or by full path names, for example:
`include " . . / . . /primitives.v"
At compile time, this line is replaced by the contents of the file "../../primitives.v".
3.5.5 `resetall
This compiler directive resets all compilation instructions to their default values.
`resetall
For example, this directive makes the default connection type a wire network type.
3.5.6 `timescale
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